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i table of contents lcd segment / common driver with controller ..................................................................... 1 features ....................................................................................................................... ............................ 1 ordering information ........................................................................................................... ............. 2 block diagram .................................................................................................................. ..................... 3 die pad arrangement ............................................................................................................ .............. 4 die pad arrangement ............................................................................................................ .............. 4 pin description................................................................................................................ ....................... 6 mstat.......................................................................................................................... ........................... 6 m .............................................................................................................................. ................................ 7 cl ............................................................................................................................. ............................... 7 dof dof ............................................................................................................................... ................... 7 1 cs , cs2 .......................................................................................................................... ...................... 7 res res ............................................................................................................................... .................. 7 sa0, scl, sda out , sda in ........................................................................................................................ 7 v dd ............................................................................................................................... ............................ 7 v ss ............................................................................................................................... ............................. 7 v ss1 ............................................................................................................................... ........................... 7 v ee ............................................................................................................................... ............................. 7 c 1p , c 1n , c 2n , c 2p c 3n and c 4n ................................................................................................................. 7 v l2 , v l3 , v l4 and v l5 ............................................................................................................................... .8 v l6 ............................................................................................................................... ............................. 8 m/ s ............................................................................................................................... .......................... 8 v f ............................................................................................................................... .............................. 8 cls ............................................................................................................................ .............................. 8 1 iic , iic2 ......................................................................................................................... ........................ 8
ii c1, c0 ......................................................................................................................... ............................. 9 row0 - row63 ................................................................................................................... ................... 9 seg0 - seg103.................................................................................................................. ..................... 9 icons.......................................................................................................................... ............................ 9 irs ............................................................................................................................ ............................... 9 test0-test7 .................................................................................................................... ..................... 9 nc/t0 ? t6 ..................................................................................................................... ......................... 9 functional block descriptions.................................................................................................. .11 iic communication interface .................................................................................................... .......... 11 command decoder ................................................................................................................ .............. 11 graphic display data ram (gddram).............................................................................................. 11 lcd driving voltage generator and regulator ................................................................................ 13 oscillator circuit ............................................................................................................. ..................... 15 reset circuit .................................................................................................................. ....................... 16 display data latch............................................................................................................. .................. 16 hv buffer cell (level shifter)................................................................................................. ............. 16 level selector................................................................................................................. ...................... 16 lcd panel driving waveform ..................................................................................................... ........ 17 command table .................................................................................................................. .................. 17 command table .................................................................................................................. .................. 18 i 2 c-bus write data and read register status ...................................................................................... 21 command descriptions ........................................................................................................... .......... 24 set lower column address ....................................................................................................... ......... 24 set higher column address ...................................................................................................... ......... 24 set internal regulator resistors ratio ......................................................................................... ..... 24 set power control register ..................................................................................................... ........... 24 set display start line ......................................................................................................... ................. 24 set contrast control register .................................................................................................. .......... 24 set segment re-map ............................................................................................................. .............. 25
iii set lcd bias ................................................................................................................... ..................... 25 set entire display on/off ...................................................................................................... .............. 25 set normal/inverse display ..................................................................................................... ........... 25 set display on/off ............................................................................................................. .................. 25 set page address ............................................................................................................... ................. 25 set com output scan direction.................................................................................................. ....... 25 set read-modify-write mode ..................................................................................................... ......... 25 software reset ................................................................................................................. .................... 26 set end of read-modify-write mode.............................................................................................. .... 26 set indicator on/off ........................................................................................................... .................. 26 nop ............................................................................................................................ ........................... 26 set test mode.................................................................................................................. ..................... 26 set power save mode............................................................................................................ .............. 26 extended commands.............................................................................................................. ....... 26 set multiplex ratio............................................................................................................ ................... 27 set bias ratio................................................................................................................. ...................... 27 set temperature coefficient (tc) value ......................................................................................... ... 27 modify oscillator frequency .................................................................................................... .......... 27 set 1/4 bias ratio............................................................................................................. .................... 27 set total frame phases ......................................................................................................... ............. 27 set display offset ............................................................................................................. ................... 28 enable band gap reference circuit .............................................................................................. .... 28 maximum ratings ................................................................................................................ ................. 30 dc characteristics............................................................................................................. ............... 31 ac characteristics............................................................................................................. ............... 33 application examples ........................................................................................................... ............ 36 initialization routine ......................................................................................................... ............... 39
solomon systech limited solomon systech limited solomon systech limited solomon systech limited semiconductor technical data this document contains information on a new product. specification and information herein are subject to change without notice. copyright ? 2003 solomon systech limited rev 1.3 01/2003 ssd0817 advance information cmos lcd segment / common driver with controller ssd0817 is a single-chip cmos lcd driver with controllers for dot-matrix graphic liquid crystal display system. it consists of 169 high-voltage driving outputs for driving maximum 104 segments, 64 commons and 1 icon line. ssd0817 consists of 104 x 65 bits graphic display data ram (gddram). data/commands are sent from common mcu through i 2 c-bus interface. ssd0817 embeds dc-dc converter with booster capacitors, on-chip oscillator and bias divider so as to reduce the number of external components. with the advanced design for low power consumption, stable lcd operating voltage and flexible die layout, ssd0817 is suitable for any portable battery-driven applications requiring long operation period with compact size. features 104 x 64 + 1 icon line single supply operation, 2.4 v - 3.5v minimum -12.0v lcd driving output voltage low current sleep mode on-chip voltage generator or external lcd driving power supply selectable 2x / 3x / 4x/ 5x on-chip dc-dc converter on-chip oscillator on-chip bias divider programmable bias ratio [1/4 ? 1/9] i 2 c-bus interface on-chip 104 x 65 graphic display data ram row re-mapping and column re-mapping vertical scrolling display offset control 64 levels internal contrast control & external contrast control programmable mux ratio [2-64 mux] (partial display mode) programmable lcd driving voltage temperature coefficients available in gold bump die
solomon rev 1 . 3 01/2003 ssd0817 series 2 ordering information table 1 - ordering information ordering part number seg com default bias package form reference SSD0817Z 104 64 + 1 1/9, 1/7 gold bump die
ssd0817 series rev 1.3 01/2003 solomon 3 block diagram figure 1 ? ssd0817 block diagram icons row0 ~ row63 seg0 ~seg103 hv buffer cell level shifter display data latch gddram 104 x 65 bits display timing generator oscillator level selector command decoder iic communication interface mstat m dof m/s cl cls v ss v dd c 0 c 1 v l6 v l5 v l4 v l3 v l2 v dd v ee v ss1 c 4n c 3n c 1p c 1n c 2n c 2p irs /res /iic1 sa 0 scl sda in sda out /cs1 cs2 iic2 test pins (test0 -test7), (t0 - t6) lcd driving voltage generator 2x/ 3x/ 4x/ 5x dc/ dc converter, voltage regulator, contrast control, bias divider with integrated capacitors, temperature compensation v f
solomon rev 1 . 3 01/2003 ssd0817 series 4 die pad arrangement figure 2 ? ssd0817 pin assignment gold bump alignment mark this alignment mark contains gold bump for ic bumping process alignment and ic identifications. no conductive tracks should be laid underneath this mark to avoid shor t circuit. note: 1. the gold bumps face up in this diagram 2. all dimensions in m and (0,0) is the center of the chip die size: 8.66 mm x 1.48 mm die thickness: 550 +/- 25 um bump pitch: 60 um [min] bump height: nominal 18 um tolerance < 4 um within die < 8 um within lot pin # 1 (-3878.7, 237.475) x 35 8.75 26.25 26.25 26.25 x center (-3876.1625, 323.6625) 26.25 26.25 26.25 26.25 52.5 x center (2751.9625, 323.6625) 26.25 26.25 26.25 16.8 13.65 12.6 center (3875.55, 149.275) 16.8 13.65 12.6 73.5 73.5 x 8 .7 5 (2755.725, 237.475) 35 t5 t4 vf iic2 vss irs vdd c1 vss c0 vdd /iic1 test7 vss cls m/s vdd t6 vl6 vl6 vl6 vl5 vl5 vl5 vl4 vl4 vl4 vee vl3 vl3 vl3 vl2 vl2 vl2 vee c4n c4n c4n c2p c2p c2p c2n c2n c2n vee c1n c1n c1n c1p c1p c1p c3n c3n c3n t2 vee vee vee vee vee vee vss1 vss1 vss1 vss1 vss1 vss vss vss t1 t0 vdd vdd vdd vdd vdd vdd vdd test6 test5 sa0 scl test4 test3 sda in sda out vdd test2 test1 vss test0 vee vee /res vdd cs2 /cs1 vss /dof cl m mstat nc row11 row12 row13 row14 row15 row16 row17 row18 row19 row20 row21 row22 row23 row24 row25 row26 row27 row28 row29 row30 row31 nc row10 row9 row8 row7 row6 row5 row4 row3 row2 row1 row0 icons seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 seg100 seg101 seg102 seg103 row32 row33 row34 row35 row36 row37 row38 row39 row40 row41 row42 row43 254 255 1 center: 2751.9625, 323.6625 center: -3876.1625, 323.6625 center: -3875.55, 149.275 size: 88.2 x 88.2 277 276 126 125 104 103 (-3878.7, 237.475) (2755.725, 237.475)
ssd0817 series rev 1.3 01/2003 solomon 5 table 2 ? ssd0817 series bump die pad coordinates (bump center) pad # signal x-pos y-pos pad # signal x-pos y-pos pad # signal x-pos y-pos 1 mstat -3873.80 -581.35 51 c3n -27.48 -581.35 101 t4 3799.95 -581.35 2 m -3797.50 -581.35 52 c1p 48.83 -581.35 102 t5 3876.25 -581.35 3 cl -3721.20 -581.35 53 c1p 125.13 -581.35 103 nc 4178.48 -655.03 4 /dof -3644.90 -581.35 54 c1p 201.43 -581.35 104 row31 4178.48 -594.83 5 vss -3568.60 -581.35 55 c1n 277.73 -581.35 105 row30 4178.48 -534.63 6 /cs1 -3492.30 -581.35 56 c1n 354.03 -581.35 106 row29 4178.48 -474.43 7 cs2 -3416.00 -581.35 57 c1n 430.33 -581.35 107 row28 4178.48 -414.23 8 vdd -3339.70 -581.35 58 vee 506.63 -581.35 108 row27 4178.48 -354.03 9 /res -3263.40 -581.35 59 c2n 582.93 -581.35 109 row26 4178.48 -293.83 10 vee -3178.35 -581.35 60 c2n 659.23 -581.35 110 row25 4178.48 -233.63 11 vee -3102.05 -581.35 61 c2n 735.53 -581.35 111 row24 4178.48 -173.43 12 test0 -3017.00 -581.35 62 c2p 811.83 -581.35 112 row23 4178.48 -113.23 13 vss -2940.70 -581.35 63 c2p 888.13 -581.35 113 row22 4178.48 -53.03 14 test1 -2864.40 -581.35 64 c2p 964.43 -581.35 114 row21 4178.48 7.18 15 test2 -2788.10 -581.35 65 c4n 1040.73 -581.35 115 row20 4178.48 67.38 16 vdd -2711.80 -581.35 66 c4n 1117.03 -581.35 116 row19 4178.48 127.58 17 sda out -2635.50 -581.35 67 c4n 1193.33 -581.35 117 row18 4178.48 187.78 18 sda in -2557.63 -581.35 68 vee 1269.63 -581.35 118 row17 4178.48 247.98 19 test3 -2481.33 -581.35 69 vl2 1345.93 -581.35 119 row16 4178.48 308.18 20 test4 -2403.10 -581.35 70 vl2 1422.23 -581.35 120 row15 4178.48 368.38 21 scl -2325.23 -581.35 71 vl2 1498.53 -581.35 121 row14 4178.48 428.58 22 sa0 -2248.93 -581.35 72 vl3 1574.83 -581.35 122 row13 4178.48 488.78 23 test5 -2172.63 -581.35 73 vl3 1651.13 -581.35 123 row12 4178.48 548.98 24 test6 -2096.33 -581.35 74 vl3 1727.43 -581.35 124 row11 4178.48 609.18 25 vdd -2020.03 -581.35 75 vee 1803.73 -581.35 125 nc 4178.48 663.25 26 vdd -1943.73 -581.35 76 vl4 1880.03 -581.35 126 row10 3834.60 587.83 27 vdd -1867.43 -581.35 77 vl4 1956.33 -581.35 127 row9 3774.40 587.83 28 vdd -1791.13 -581.35 78 vl4 2032.63 -581.35 128 row8 3714.20 587.83 29 vdd -1714.83 -581.35 79 vl5 2108.93 -581.35 129 row7 3654.00 587.83 30 vdd -1638.53 -581.35 80 vl5 2185.23 -581.35 130 row6 3593.80 587.83 31 vdd -1562.23 -581.35 81 vl5 2261.53 -581.35 131 row5 3533.60 587.83 32 t0 -1485.93 -581.35 82 vl6 2337.83 -581.35 132 row4 3473.40 587.83 33 t1 -1409.63 -581.35 83 vl6 2414.13 -581.35 133 row3 3413.20 587.83 34 vss -1333.33 -581.35 84 vl6 2490.60 -581.35 134 row2 3353.00 587.83 35 vss -1257.03 -581.35 85 t6 2566.73 -581.35 135 row1 3292.80 587.83 36 vss -1180.73 -581.35 86 vdd 2651.78 -581.35 136 row0 3232.60 587.83 37 vss1 -1095.68 -581.35 87 m/s 2728.08 -581.35 137 icons 3172.40 587.83 38 vss1 -1019.38 -581.35 88 cls 2804.38 -581.35 138 seg0 3112.20 587.83 39 vss1 -943.08 -581.35 89 vss 2880.68 -581.35 139 seg1 3052.00 587.83 40 vss1 -866.78 -581.35 90 test7 2956.98 -581.35 140 seg2 2991.80 587.83 41 vss1 -790.48 -581.35 91 /iic1 3033.28 -581.35 141 seg3 2931.60 587.83 42 vee -714.18 -581.35 92 vdd 3109.58 -581.35 142 seg4 2871.40 587.83 43 vee -637.88 -581.35 93 c0 3185.88 -581.35 143 seg5 2811.20 587.83 44 vee -561.58 -581.35 94 vss 3262.18 -581.35 144 seg6 2751.00 587.83 45 vee -485.28 -581.35 95 c1 3338.48 -581.35 145 seg7 2690.80 587.83 46 vee -408.98 -581.35 96 vdd 3414.78 -581.35 146 seg8 2630.60 587.83 47 vee -332.68 -581.35 97 irs 3491.08 -581.35 147 seg9 2570.40 587.83 48 t2 -256.38 -581.35 98 vss 3567.38 -581.35 148 seg10 2510.20 587.83 49 c3n -180.08 -581.35 99 iic2 3643.68 -581.35 149 seg11 2450.00 587.83 50 c3n -103.78 -581.35 100 vf 3723.65 -581.35 150 seg12 2389.80 587.83
solomon rev 1 . 3 01/2003 ssd0817 series 6 pad # signal x-pos y-pos pad # signal x-pos y-pos pad # signal x-pos y-pos 151 seg13 2329.60 587.83 201 seg63 -680.40 587.83 251 row41 -3690.40 587.83 152 seg14 2269.40 587.83 202 seg64 -740.60 587.83 252 row42 -3750.60 587.83 153 seg15 2209.20 587.83 203 seg65 -800.80 587.83 253 row43 -3810.80 587.83 154 seg16 2149.00 587.83 204 seg66 -861.00 587.83 254 nc -4178.48 663.25 155 seg17 2088.80 587.83 205 seg67 -921.20 587.83 255 row44 -4178.48 609.18 156 seg18 2028.60 587.83 206 seg68 -981.40 587.83 256 row45 -4178.48 548.98 157 seg19 1968.40 587.83 207 seg69 -1041.60 587.83 257 row46 -4178.48 488.78 158 seg20 1908.20 587.83 208 seg70 -1101.80 587.83 258 row47 -4178.48 428.58 159 seg21 1848.00 587.83 209 seg71 -1162.00 587.83 259 row48 -4178.48 368.38 160 seg22 1787.80 587.83 210 seg72 -1222.20 587.83 260 row49 -4178.48 308.18 161 seg23 1727.60 587.83 211 seg73 -1282.40 587.83 261 row50 -4178.48 247.98 162 seg24 1667.40 587.83 212 seg74 -1342.60 587.83 262 row51 -4178.48 187.78 163 seg25 1607.20 587.83 213 seg75 -1402.80 587.83 263 row52 -4178.48 127.58 164 seg26 1547.00 587.83 214 seg76 -1463.00 587.83 264 row53 -4178.48 67.38 165 seg27 1486.80 587.83 215 seg77 -1523.20 587.83 265 row54 -4178.48 7.18 166 seg28 1426.60 587.83 216 seg78 -1583.40 587.83 266 row55 -4178.48 -53.03 167 seg29 1366.40 587.83 217 seg79 -1643.60 587.83 267 row56 -4178.48 -113.23 168 seg30 1306.20 587.83 218 seg80 -1703.80 587.83 268 row57 -4178.48 -173.43 169 seg31 1246.00 587.83 219 seg81 -1764.00 587.83 269 row58 -4178.48 -233.63 170 seg32 1185.80 587.83 220 seg82 -1824.20 587.83 270 row59 -4178.48 -293.83 171 seg33 1125.60 587.83 221 seg83 -1884.40 587.83 271 row60 -4178.48 -354.03 172 seg34 1065.40 587.83 222 seg84 -1944.60 587.83 272 row61 -4178.48 -414.23 173 seg35 1005.20 587.83 223 seg85 -2004.80 587.83 273 row62 -4178.48 -474.43 174 seg36 945.00 587.83 224 seg86 -2065.00 587.83 274 row63 -4178.48 -534.63 175 seg37 884.80 587.83 225 seg87 -2125.20 587.83 275 icons -4178.48 -594.83 176 seg38 824.60 587.83 226 seg88 -2185.40 587.83 276 nc -4178.48 -655.03 177 seg39 764.40 587.83 227 seg89 -2245.60 587.83 277 nc -3875.55 149.28 179 seg41 644.00 587.83 229 seg91 -2366.00 587.83 180 seg42 583.80 587.83 230 seg92 -2426.20 587.83 181 seg43 523.60 587.83 231 seg93 -2486.40 587.83 182 seg44 463.40 587.83 232 seg94 -2546.60 587.83 183 seg45 403.20 587.83 233 seg95 -2606.80 587.83 184 seg46 343.00 587.83 234 seg96 -2667.00 587.83 185 seg47 282.80 587.83 235 seg97 -2727.20 587.83 bump size 186 seg48 222.60 587.83 236 seg98 -2787.40 587.83 pad# x [um] y [um] 187 seg49 162.40 587.83 237 seg99 -2847.60 587.83 1 ? 102 50.05 50.05 188 seg50 102.20 587.83 238 seg100 -2907.80 587.83 103 ? 124 66.675 40.95 189 seg51 42.00 587.83 239 seg101 -2968.00 587.83 125 66.675 28.7 190 seg52 -18.20 587.83 240 seg102 -3028.20 587.83 126 ? 253 40.95 66.675 191 seg53 -78.40 587.83 241 seg103 -3088.40 587.83 254 66.675 28.7 192 seg54 -138.60 587.83 242 row32 -3148.60 587.83 255 ? 276 66.675 40.95 193 seg55 -198.80 587.83 243 row33 -3208.80 587.83 277 88.2 88.2 195 seg57 -319.20 587.83 245 row35 -3329.20 587.83 196 seg58 -379.40 587.83 246 row36 -3389.40 587.83 197 seg59 -439.60 587.83 247 row37 -3449.60 587.83 198 seg60 -499.80 587.83 248 row38 -3509.80 587.83 199 seg61 -560.00 587.83 249 row39 -3570.00 587.83 200 seg62 -620.20 587.83 250 row40 -3630.20 587.83 pin description mstat this pin is the static indicator driving output. it is only active in master operation. the frame signal output pin, m, should be used as the back plane signal for the static indicator. the duration of overlapping can be programmable. this pin, mstat, becomes high impedance if the chip is operating in slave mode. please see the extended command table for reference.
ssd0817 series rev 1.3 01/2003 solomon 7 m this pin is the frame signal input/output. in master mode, this pin supplies the frame signal to slave devices. in slave mode, this pin receives the frame signal from the master device. cl this pin is the system clock input/output. when both the internal oscillator (cls pin pulled high) and the master mode (m/s pin pulled high) are enabled, the cl pin will supplies system clock signal to the slave device. when both internal oscillator and the slave mode are enabled, the cl pin receives system clock signal from either the master device or the external clock source. dof dof this pin is the display blanking signal control pin. in master mode, the dof pin supplies ?display on? or ?display off? signal (blanking signal) to the slave devices. in slave mode, the dof pin receives ?display on? or ?display off? signal from the master device. 1 cs , cs2 these pins are the chip selection inputs. the chip is enabled for mcu communication only when 1 cs is pulled low and cs2 is pulled high. res res this pin is the reset signal input. initialization of the chip is started once the reset pin is pulled low. the minimum pulse width for completion of the reset procedure is 5 -10 us. sa0, scl, sda out , sda in these pins are bi-directional data bus to be connected to the mcu in i 2 c-bus interface. please refer to the section: i 2 c communication interface on page 11 for detail pin descriptions. v dd the v dd is the chip?s power supply pins. v dd is also acted as a reference level of both the dc-dc converter and the lcd driving output. v ss the v ss is the grounding of the chip. v ss is also acted as a reference level of the logic input/output. v ss1 the v ss1 is the input of the internal dc-dc converter. the generated voltage from the internal dc-dc converter, v ee , is equal to the multiple factors (2x, 3x, 4x, 5x) times the potential different between v ss1 , and v dd . the multiple factors, 2x, 3x, 4x or 5x are selected by different arrangements of the external boosting capacitors. note: the potential at this input pin must lower than or equal to v ss . v ee this is the most negative voltage supply pin of the chip. it can be supplied externally or generated by the internal dc-dc converter. if the internal dc-dc converter generates the voltage level at v ee , the voltage level is used for internal referencing only. the voltage level at v ee pins is not used for driving external circuitry. c 1p , c 1n , c 2n , c 2p c 3n and c 4n when internal dc-dc voltage converter is used, external capacitor(s) is/are connected between these pins. different connections result in different dc-dc converter multiple factors, for example, 2x, 3x, 4x or 5x. please refer to the voltage converter section in the functional block description for detail description.
solomon rev 1 . 3 01/2003 ssd0817 series 8 v l2 , v l3 , v l4 and v l5 these pins are outputs with voltage levels equal to the lcd driving voltage. all these voltage levels are referenced to v dd . the voltage levels can be supplied externally or generated by the internal bias divider. the bias divider is turned on once the output op-amp buffers are enabled. please refer to the set power control register command for detail description. the voltage potential relationship is given as: v dd > v l2 > v l3 > v l4 > v l5 > v l6 in addition, assume the bias factor is known as a, vl2 - vdd = 1/a * (vl6 - vdd) vl3 - vdd = 2/a * (vl6 - vdd) vl4 - vdd = (a-2)/a * (vl6 - vdd) vl5 - vdd = (a-1)/a * (vl6 - vdd) v l6 this pin outputs the most negative lcd driving voltage level. the v l6 can be supplied externally or generated by the internal regulator. please refer to the set power control register command for detail description. m/ s this pin is the master/slave mode selection input. when this pin is pulled high, master mode is selected. cl, m, mstat and dof signals will become output pins of the slave devices. when this pin is pulled low, slave mode is selected. cl, m, dof will become input pins. the cl, m, dof signals are received from the master device. the mstat pin will stay at high impedance state. v f this pin is the input of the built-in voltage regulator for generating v l6 . when external resistor network is selected (irs pulled low) to generate the lcd driving level, v l6 , two external resistors should be added. r 1 should be connected between v dd and v f . r 2 should be connected between v f and v l6. cls this pin is the internal clock enable pin. when this pin is pulled high, the internal clock is enabled. the internal clock will be disabled when cls is pulled low. under such circumstances, an external clock source must be fed into the cl pin. 1 iic , iic2 these pins are i 2 c-bus interface selection inputs. the iic communication interface is enabled only when 1 iic is pulled low and iic2 is pulled high.
ssd0817 series rev 1.3 01/2003 solomon 9 c1, c0 these two pins are the chip mode selection input. the chip mode is determined by multiplex ratio. altogether there are four chip modes. please see the following list for reference. c1 c0 chip mode 0 0 48 mux mode 0 1 54 mux mode 1 0 32 mux mode 1 1 64 mux mode row0 - row63 these pins provide the driving signals, common, to the lcd panel. please refer to the table 3 on page 10 for the com signal mapping in different mux. seg0 - seg103 these pins provide the lcd driving signals, segment, to the lcd panel. the output voltage level of these pins is v dd during sleep mode or standby mode. icons there are two icons pins (pin137 and 275) on the chip. both pins output exactly the same signal. the duplicated icon pins will enhance the flexibility of the lcd layout. irs this is the input pin to enable the internal resistors network for the voltage regulator. when this pin is pulled high, the internal feedback resistors of the internal regulator for generating v l6 will be enabled. when it is pulled low, external resistors, r 1 should be connected to v dd and v f . r 2 should be connected between v f and v l6 , respectively. test0-test7 these are input pins that reserved for testing purpose. these pins should be connected to vdd. nc/t0 ? t6 these are the no connection pins. these pins should be left open and they are prohibited to have any connections with one another.
solomon rev 1 . 3 01/2003 ssd0817 series 10 table 3 - example of row pin assignment for different programmable mux of ssd0817 48 mux mode 54 mux mode 32 mux mode 64 mux mode row0 com0 com0 com0 com0 row1 com1 com1 com1 com1 row2 com2 com2 com2 com2 row3 com3 com3 com3 com3 row4 com4 com4 com4 com4 row5 com5 com5 com5 com5 row6 com6 com6 com6 com6 row7 com7 com7 com7 com7 row8 com8 com8 com8 com8 row9 com9 com9 com9 com9 row10 com10 com10 com10 com10 row11 com11 com11 com11 com11 row12 com12 com12 com12 com12 row13 com13 com13 com13 com13 row14 com14 com14 com14 com14 row15 com15 com15 com15 com15 row16 com16 com16 nc com16 row17 com17 com17 nc com17 row18 com18 com18 nc com18 row19 com19 com19 nc com19 row20 com20 com20 nc com20 row21 com21 com21 nc com21 row22 com22 com22 nc com22 row23 com23 com23 nc com23 row24 nc com24 nc com24 row25 nc com25 nc com25 row26 nc com26 nc com26 row27 nc nc nc com27 row28 nc nc nc com28 row29 nc nc nc com29 row30 nc nc nc com30 row31 nc nc nc com31 row32 com24 com27 com16 com32 row33 com25 com28 com17 com33 row34 com26 com29 com18 com34 row35 com27 com30 com19 com35 row36 com28 com31 com20 com36 row37 com29 com32 com21 com37 row38 com30 com33 com22 com38 row39 com31 com34 com23 com39 row40 com32 com35 com24 com40 row41 com33 com36 com25 com41 row42 com34 com37 com26 com42 row43 com35 com38 com27 com43 row44 com36 com39 com28 com44 row45 com37 com40 com29 com45 row46 com38 com41 com30 com46 row47 com39 com42 com31 com47 row48 com40 com43 nc com48 row49 com41 com44 nc com49 row50 com42 com45 nc com50 row51 com43 com46 nc com51 row52 com44 com47 nc com52 row53 com45 com48 nc com53 row54 com46 com49 nc com54 row55 com47 com50 nc com55 row56 nc com51 nc com56 row57 nc com52 nc com57 row58 nc com53 nc com58 row59 nc nc nc com59 row60 nc nc nc com60 row61 nc nc nc com61 row62 nc nc nc com62 row63 nc nc nc com63 (note: x - output non-selected com signal)
ssd0817 series rev 1.3 01/2003 solomon 11 functional block descriptions iic communication interface the iic communication interface consists of slave address bit (sa0), i 2 c-bus data signal (sda) and i 2 c-bus clock signal (scl). both the sda and the scl must be connected to pull-up resistors. there are also five input signals including, res , 1 cs , iic1 , cs2, iic2, which is used for the initialization of device. a) slave address bit (sa0) ssd0817 have to recognize the slave address before transmitting or receiving any information by the i 2 c-bus. the device will responds to the slave address following by the slave address bit (?sa0? bit) and the read/write select bit (? r/ w ? bit) with the following byte format, b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 1 1 1 0 sa0 r/ w ?sa0? bit provides an extension bit for the slave address. either ?0111100? or ?0111101?, can be selected as the slave address of ssd0817. ? r/ w ? bit determines the i 2 c-bus interface is operating at either write mode or read status mode. b) i 2 c-bus data signal (sda) sda acts as a communication channel between the transmitter and the receiver. the data and the acknowledgement are sent through the sda. if sda in is connected to the ?sda out?, the device becomes fully iic bus compatible. it should be noticed that the ito track resistance and the pulled-up resistance at ?sda? pin becomes a voltage potential divider. as a result, the acknowledgement would not be possible to attain a valid logic 0 level in ?sda?. the ?sda out? pin may be disconnected from the ?sda in? pin. with such arrangement, the acknowledgement signal will be ignored in the i 2 c-bus. c) i 2 c-bus clock signal (scl) the transmission of information in the i 2 c-bus is following a clock signal, scl. each transmission of data bit is taken place during a single clock period of scl. command decoder input is directed to the command decoder based on the input of control byte which consists of a d/ c bit and a r/ w bit. for further information about the control byte, please refer to the section ?i 2 c- bus write data and read register status? on page 21. if both the d/ c bit and the r/ w bit are low, the input signal is interpreted as a command. it will be decoded and written to the corresponding command register. if the d/ c bit is high and the r/ w bit is low, input signal is written to graphic display data ram (gddram). graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is 104 x 65 = 6760 bits. table 4 on page 12 is a description of the gddram address map. for mechanical flexibility, re-mapping on both segment and common outputs can be selected by software. during the vertical scrolling of the display, an internal register (display start line register) stores the address of the display start line. the re-mapping operation can be started at the address of the display start line according to the internal register. table 4 on page 12 shows the case in which the display start line register is set to 38h. for those gddram out of the display common range, they can be accessed for either the preparation of vertical scrolling data or the system usage.
solomon rev 1 . 3 01/2003 ssd0817 series 12 normal 00h 01h 02h 03h ? ? ? ? ? ? 64h 65h 66h 67h remapped 67h 66h 65h 64h ? ? ? ? ? ? 03h 02h 01h 00h 00h d0 (lsb) ? ? ? ? ? ? 8 39 8 45 8 23 8 55 01h d1 ? ? ? ? ? ? 9 38 9 44 9 22 9 54 02h d2 ? ? ? ? ? ? 1037104310211053 03h d3 ? ? ? ? ? ? 1136114211201152 04h d4 ? ? ? ? ? ? 1235124112191251 05h d5 ? ? ? ? ? ? 1334134013181350 06h d6 ? ? ? ? ? ? 1433143914171449 07h d7 (msb) ? ? ? ? ? ? 15 32 15 38 15 16 15 48 08h d0 (lsb) ? ? ? ? ? ? 16 31 16 37 16 15 16 47 09h d1 ? ? ? ? ? ? 1730173617141746 0ah d2 ? ? ? ? ? ? 1829183518131845 0bh d3 ? ? ? ? ? ? 1928193419121944 0ch d4 ? ? ? ? ? ? 2027203320112043 0dh d5 ? ? ? ? ? ? 2126213221102142 0eh d6 ? ? ? ? ? ? 22 25 22 31 22 9 22 41 0fh d7 (msb) ? ? ? ? ? ? 23 24 23 30 23 8 23 40 10h d0 (lsb) ? ? ? ? ? ? 24 23 24 29 24 7 24 39 11h d1 ? ? ? ? ? ? 25 22 25 28 25 6 25 38 12h d2 ? ? ? ? ? ? 26 21 26 27 26 5 26 37 13h d3 ? ? ? ? ? ? 27 20 27 26 27 4 27 36 14h d4 ? ? ? ? ? ? 28 19 28 25 28 3 28 35 15h d5 ? ? ? ? ? ? 29 18 29 24 29 2 29 34 16h d6 ? ? ? ? ? ? 30 17 30 23 30 1 30 33 17h d7 (msb) ? ? ? ? ? ? 31 16 31 22 31 0 31 32 18h d0 (lsb) ? ? ? ? ? ? 32 15 32 21 x x 32 31 19h d1 ? ? ? ? ? ? 33 14 33 20 x x 33 30 1ah d2 ? ? ? ? ? ? 34 13 34 19 x x 34 29 1bh d3 ? ? ? ? ? ? 35 12 35 18 x x 35 28 1ch d4 ? ? ? ? ? ? 36 11 36 17 x x 36 27 1dh d5 ? ? ? ? ? ? 37 10 37 16 x x 37 26 1eh d6 ? ? ? ? ? ? 38 9 38 15 x x 38 25 1fh d7 (msb) ? ? ? ? ? ? 39 8 39 14 x x 39 24 20h d0 (lsb) ? ? ? ? ? ? 40 7 40 13 x x 40 23 21h d1 ? ? ? ? ? ? 41 6 41 12 x x 41 22 22h d2 ? ? ? ? ? ? 42 5 42 11 x x 42 21 23h d3 ? ? ? ? ? ? 43 4 43 10 x x 43 20 24h d4 ? ? ? ? ? ? 44 3 44 9 x x 44 19 25h d5 ? ? ? ? ? ? 45 2 45 8 x x 45 18 26h d6 ? ? ? ? ? ? 46 1 46 7 x x 46 17 27h d7 (msb) ? ? ? ? ? ? 47 0 47 6 x x 47 16 28h d0 (lsb) ? ? ? ? ? ? x x 48 5 x x 48 15 29h d1 ? ? ? ? ? ? x x 49 4 x x 49 14 2ah d2 ? ? ? ? ? ? x x 50 3 x x 50 13 2bh d3 ? ? ? ? ? ? x x 51 2 x x 51 12 2ch d4 ? ? ? ? ? ? x x 52 1 x x 52 11 2dh d5 ? ? ? ? ? ? x x 53 0 x x 53 10 2eh d6 ? ? ? ? ? ? xxxxxx549 2fh d7 (msb) ? ? ? ? ? ? xxxxxx558 30h d0 (lsb) ? ? ? ? ? ? xxxxxx567 31h d1 ? ? ? ? ? ? xxxxxx576 32h d2 ? ? ? ? ? ? xxxxxx585 33h d3 ? ? ? ? ? ? xxxxxx594 34h d4 ? ? ? ? ? ? xxxxxx603 35h d5 ? ? ? ? ? ? xxxxxx612 36h d6 ? ? ? ? ? ? xxxxxx621 37h d7 (msb) ? ? ? ? ? ? xxxxxx630 38h d0 (lsb) ? ? ? ? ? ? 0 47 0 53 0 31 0 63 39h d1 ? ? ? ? ? ? 1 46 1 52 1 30 1 62 3ah d2 ? ? ? ? ? ? 2 45 2 51 2 29 2 61 3bh d3 ? ? ? ? ? ? 3 44 3 50 3 28 3 60 3ch d4 ? ? ? ? ? ? 4 43 4 49 4 27 4 59 3dh d5 ? ? ? ? ? ? 5 42 5 48 5 26 5 58 3eh d6 ? ? ? ? ? ? 6 41 6 47 6 25 6 57 3fh d7 (msb) ? ? ? ? ? ? 7 40 7 46 7 24 7 56 page 8 d0 (lsb) ? ? ? ? ? ? icons icons icons icons icons icons icons icons segment pins 0 1 2 3 ? ? ? ? ? ? 100 101 102 103 page 6 page 7 normal remapped page 2 page 3 page 4 page 5 page 0 page 1 normal remapped normal remapped ram row ram column normal remapped common pins 48 mux mode 54 mux mode 32 mux mode 64 mux mode remarks : db0 ? db7 represent the data bit of the gddram table 4 - graphic display data ram (gddram) address map with display start line set to 38h lcd driving voltage generator and regulator
ssd0817 series rev 1.3 01/2003 solomon 13 lcd driving voltage generator and regulator this module generates the lcd voltage required for display driving output. with reference to v dd , it takes a single supply input, v ss , and generates all the necessary voltage levels. this block consists of: 1. 2x, 3x, 4x and 5x dc-dc voltage converter the built-in dc-dc voltage converter is used to generate the negative voltage with reference to vdd from the voltage input (vss1). for ssd0817, it is possible to produce 2x, 3x, 4x or 5x boosting from the potential different between v ss1 - v dd . detailed configurations of the dc-dc converter for different boosting multiples are given in figure 3. figure 3 - dc-dc converter configurations 2. voltage regulator (voltages referenced to v dd ) internal (irs pin = h) feedback gain can control the lcd driving contrast curves. if internal resistor network is enabled, eight settings can be selected through software command. if external control is selected, external resistors are connected between v dd and v f (r1), and between v f and v l6 (r2). 3. contrast control (voltage referenced to v dd ) software control of the 64-contrast voltage levels at each voltage regulator feedback gain. the equation of calculating the lcd driving voltage is given as: ssd0817 5x boostin g confi g uration v ss1 v ee c 3n c 1p c 1n c 2n c 2p c 4n c1 + + + c1 c1 c1 + + c1 4x boostin g confi g uration v ss1 v ee c 3n c 1p c 1n c 2n c 2p c 4n c1 + + + c1 c1 + ssd0817 3x boostin g confi g uration v ss1 v ee c 3n c 1p c 1n c 2n c 2p c 4n c1 + + c1 c1 + ssd0817 2x boostin g confi g uration v ss1 v ee c 3n c 1p c 1n c 2n c 2p c 4n c1 + + c1 ssd0817 remarks: 1. c1= 0.47 ? 4.7uf 2. boosting input from vss1 3. vss1 should be lower potential than or equal to vss 4. all voltages are referenced to vdd c1
solomon rev 1 . 3 01/2003 ssd0817 series 14 v l6 ?v dd = gain * [1 + (18 + )] * v ref stands for the contrast set (0 to 63) 81 gain = (1 + rb/ra), the reference value is shown in table 5. register ratio d2 d1 d0 thermal gradient = -0.07 %/ o c 0 0 0 2.92 0 0 1 3.40 0 1 0 3.89 0 1 1 4.37 1 0 0 4.85 1 0 1 5.23 1 1 0 5.72 1 1 1 6.19 table 5 gain value at different register ratio and thermal gradient settings v ref is a fixed ic?internal voltage supply and its voltage at room temperature (25 o c) is shown in table 6 for reference. type thermal gradient v ref tc 0 -0.07 %/ o c -1.08v tc 2 -0.13 %/ o c -1.12v tc 4 -0.26 %/ o c -1.09v tc 7 -0.29 %/ o c -1.10v external resistor gain mode [gain = 5.00] @ tc0 -0.07 %/ o c -1.08v table 6 v ref values at different thermal gradient settings the voltage regulator output for different gain/contrast settings is shown in figure 4. figure 4 ? voltage regulator output for different gain/contrast settings 4. bias ratio selection circuitry the bias ratios can be software selected from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9. since there will be slightly different in command pattern for different mux, please refer to command descriptions section of this data sheet. if the output op-amp buffer option in set power control register command is enabled, this circuit block will divide the regulator output (v l6 ) to give the lcd driving levels (v l2 ~ v l5 ). a low power consumption circuit design in this bias divider saves most of the display current comparing to the traditional design. stabilizing capacitors (0.1uf ~ 0.47uf) are
ssd0817 series rev 1.3 01/2003 solomon 15 ssd1815b v dd v l2 v l3 v l4 v l5 v l6 r3 r1 r2 r4 + v dd c5 + c4 + c3 + c2 + c1 remark: 1. c1 ~ c5 = 0.01 ~ 0. 47uf 2. r1 ~ r4 = 100k~ 1m ? ssd0817 required to be connected between these voltage level pins (v l2 ~ v l5 ) and (v dd ). if the lcd panel loading is heavy, four additional resistors are suggested to add to the application circuit as follows: 5. self adjust temperature compensation circuitry this block provides 4 different compensation settings to satisfy various liquid crystal temperature grades by software control. the default temperature coefficient (tc) setting is tc0. oscillator circuit this module is an on-chip low power rc oscillator circuitry (figure 5). the oscillator generates the clock for the dc-dc voltage converter. this clock is also used in the display timing generator. enable oscillation circuit enable buffer internal resistor osc2 osc1 oscillator enable (cl) figure 5 - on-chip low power rc oscillator circuitry remark: 1. c1 ~ c5 = 0.1uf ~ 0.47uf 2. r1 ~ r4 = 100k ? ~1m ?
solomon rev 1 . 3 01/2003 ssd0817 series 16 reset circuit this block includes power on reset (por) circuitry and the hardware reset pin, res . the por and hardware reset performs the same reset function. once res receives a reset pulse, all internal circuitry will start to initialize. minimum pulse width the reset sequence is 5 -10us. status of the chip after reset is given by: display is turned off default display mode 64 mux: 104 x 64 + 1 icon line normal segment and display data column address mapping (seg0 mapped to row address 00h) read-modify-write mode is off power control register is set to 000b register data clear in i 2 c-bus interface bias ratio is set to default 64 mux: 1/9 static indicator is turned off display start line is set to gddram column 0 column address counter is set to 00h page address is set to 0 normal scan direction of the com outputs contrast control register is set to 20h test mode is turned off temperature coefficient is set to tc0 display data latch this block is a series of latches carrying the display signal information. these latches hold the data, which will be fed to the hv buffer cell and level selector to output the required voltage level. the numbers of latches of different members are given by: 64 mux: 104 + 65 = 169 hv buffer cell (level shifter) hv buffer cell works as a level shifter which translates the low voltage output signal to the required driving voltage. the output is shifted out with reference to the internal frm clock which comes from the display timing generator. the voltage levels are given by the level selector which is synchronized with the internal m signal. level selector level selector is a control of the display synchronization. display voltage levels can be separated into two sets and used with different cycles. synchronization is important since it selects the required lcd voltage level to the hv buffer cell, which in turn outputs the com or seg lcd waveform.
ssd0817 series rev 1.3 01/2003 solomon 17 lcd panel driving waveform figure 6 is an example of how the common and segment drivers may be connected to a lcd panel. the waveforms illustrate the desired multiplex scheme. com1 com2 com3 com4 com5 com6 com7 e g 1 e g 2 e g 3 e g 4 com0 e g 0 time slot com0 com1 seg0 seg1 m v dd v l2 v l3 v l4 v l5 v l6 v dd v l2 v l3 v l4 v l5 v l6 v dd v l2 v l3 v l4 v l5 v l6 v dd v l2 v l3 v l4 v l5 v l6 * note 1: n+1 is the number of multiplex ratio including icon. 1 2 3 4 5 6 7 8 9 . . . n+1 * 1 2 3 4 5 6 7 8 9 . . n+1 * 1 2 3 4 5 6 7 8 9 . . n+1 * 1 2 3 4 5 6 7 8 9 . . . n+1 * figure 6 - lcd driving waveform for displaying "0"
solomon rev 1 . 3 01/2003 ssd0817 series 18 command table bit pattern command description 0000x 3 x 2 x 1 x 0 set lower column address set the lower nibble of the column address register using x 3 x 2 x 1 x 0 as data bits. the lower nibble of column address is reset to 0000b after por 0001x 3 x 2 x 1 x 0 set higher column address set the higher nibble of the column address register using x 3 x 2 x 1 x 0 as data bits. the higher nibble of column address is reset to 0000b after por. 00100x 2 x 1 x 0 set internal regulator resistor ratio feedback gain of the internal regulator generating vl6 increases as x 2 x 1 x 0 increased from 000b to 111b. after por, x 2 x 1 x 0 = 100b 00101x 2 x 1 x 0 set power control register x 0 =0: turns off the output op-amp buffer (por) x 0 =1: turns on the output op-amp buffer x 1 =0: turns off the internal regulator (por) x 1 =1: turns on the internal regulator x 2 =0: turns off the internal voltage booster (por) x 2 =1: turns on the internal voltage booster 01x 5 x 4 x 3 x 2 x 1 x 0 set display start line set gddram display start line register from 0-63 using x 5 x 4 x 3 x 2 x 1 x 0 . display start line register is reset to 000000 after por. 10000001 ** x 5 x 4 x 3 x 2 x 1 x 0 set contrast control register select contrast level from 64 contrast steps. contrast increases (vl6 decreases) as x 5 x 4 x 3 x 2 x 1 x 0 is increased from 000000b to 111111b. x 5 x 4 x 3 x 2 x 1 x 0 = 100000b after por 1010000x 0 set segment re-map x 0 =0: column address 00h is mapped to seg0 (por) x 0 =1: column address 67h is mapped to seg0 refer to table 4 on page 12 for example. 1010001x 0 set lcd bias x 0 =0: por default bias 48 mux mode: 1/8 54 mux mode: 1/8.4 32 mux mode: 1/6 64 mux mode: 1/9 x 0 =1: alternate bias 48 mux mode: 1/6 54 mux mode: 1/6 32 mux mode: 1/5 64 mux mode: 1/7 for other bias ratio settings, see ?set 1/4 bias ratio? and ?set bias ratio? in extended command set. 1010010x 0 set entire display on/off x 0 =0: normal display (por) x 0 =1: entire display on 1010011x 0 set normal/inverse display x 0 =0: normal display (por) x 0 =1: inverse display 1010111x 0 set display on/off x 0 =0: turns off lcd panel (por) x 0 =1: turns on lcd panel 1011x 3 x 2 x 1 x 0 set page address set gddram page address (0-8) for read/write using x 3 x 2 x 1 x 0 1100x 3 * * * set com output scan direction x 3 =0: normal mode (por) x 3 =1: remapped mode, com 0 to com [n-1] becomes com [n-1] to com 0 when multiplex ratio is equal to n. see figure 5 on page 17 for detail mapping. 11100000 set read-modify-write mode read-modify-write mode will be entered in which the column address will not be increased during display data read. after por, read-modify-write mode is turned off. 11100010 software reset initialize internal status registers 11101110 set end of read-modify-write mode exit read-modify-write mode. ram column address before entering the mode will be restored. after por, read-modify-write mode is off. 1010110x 0 indicator display mode this second b y te command is re q uired only when
ssd0817 series rev 1.3 01/2003 solomon 19 * * * * * * x 1 x 0 set indicator on/off ?set indicator on? command is sent. x 0 = 0: indicator off (por, second command byte is not required) x 0 = 1: indicator on (second command byte required) x 1 x 0 = 00: indicator off x 1 x 0 = 01: indicator on and blinking at ~1 second interval x 1 x 0 = 10: indicator on and blinking at ~1/2 second interval x 1 x 0 = 11: indicator on constantly 11100011 nop command result in no operation 11110000 test mode reset reserved for ic testing. do not use 1111 * * * * set test mode reserved for ic testing. do not use. 10101110 10100101 set power save mode (standby or sleep) standby or sleep mode will be entered using compound commands. issue compound commands ?set display off? followed by ?set entire display on?. table 7 - write command table (d/ c =0, r/ w =0) bit pattern command description 10101000 00x 5 x 4 x 3 x 2 x 1 x 0 set multiplex ratio to select multiplex ratio n from 2 to the maximum multiplex ratio (por value) for each member (including icon line). max. mux ratio: 64 mux: 65 n = x 5 x 4 x 3 x 2 x 1 x 0 + 2, e.g. n = 001111b + 2 = 17 10101001 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 set bias ratio (x 1 x 0 ) set tc value (x 4 x 3 x 2 ) modify osc. freq. (x 7 x 6 x 5 ) for 64 mux mode x 1 x 0 = 00(por) 01 10 11 1/9 or 1/7 1/5 1/6 1/8 for 54 mux mode x 1 x 0 = 00(por) 01 10 11 1/8.4 or 1/6 1/5 1/6 1/8 for 48 mux mode x 1 x 0 = 00(por) 01 10 11 1/8 or 1/6 1/5 1/6 1/8 for 32 mux mode x 1 x 0 = 00(por) 01 10 11 1/6 or 1/5 1/5 1/6 1/8 x 4 x 3 x 2 = 000: (tc0) typ. ?0.07%/ o c x 4 x 3 x 2 = 010: (tc1) typ. ?0.13%/ o c x 4 x 3 x 2 = 100: (tc5) typ. ?0.26%/ o c x 4 x 3 x 2 = 111: (tc7) typ. ?0.29%/ o c x 4 x 3 x 2 = 001, 011, 101, 110: reserved increase the value of x 7 x 6 x 5 will increase the oscillator frequency and vice versa. default mode: x 7 x 6 x 5 = 011 (por for 48 mux mode, 54 mux mode) : typ. 31.5khz x 7 x 6 x 5 = 011 (por for 32 mux mode, 64 mux mode) : typ. 18.7hz
solomon rev 1 . 3 01/2003 ssd0817 series 20 remarks: by software program the multiplex ratio, the typical oscillator frequency is listed above. 1010101x 0 set 1/4 bias ratio x 0 = 0: use normal setting (por) x 0 = 1: fixed at 1/4 bias regardless of other bias setting commands 11010100 00x 5 x 4 0000 set total frame phases the on/off of the static icon is given by 3 phases / 1 phase overlapping of the m and mstat signals. this command set total phases of the m/mstat signals for each frame. the more the total phases, the less the overlapping time and thus the lower the effective driving voltage. x 5 x 4 = 00: 5 phases x 5 x 4 = 01: 7 phases x 5 x 4 = 10: 9 phases (por) x 5 x 4 = 11: 16 phases 11010011 00x 5 x 4 x 3 x 2 x 1 x 0 set display offset after por, x 5 x 4 x 3 x 2 x 1 x 0 = 0 after setting mux ratio less than default value, data will be displayed at center of display matrix. to move display towards row 0 by l, x 5 x 4 x 3 x 2 x 1 x 0 = l to move display away from row 0 by l, x 5 x 4 x 3 x 2 x 1 x 0 = 64-l note: max. value of l = (por default mux ratio ? display mux)/2 11010110 001111x 1 x 0 enable band gap reference circuit x 1 x 0 = 00 01 10 11(por) 100 ms 200 ms 400 ms 800 ms approx. band gap clock period this command should execute if divider is used without capacitor at vl2 to vl5. recommendation: set the band gap clock period to approx. 200ms table 8 - extended command table note: command patterns other than that given in command table and extended command table are prohibited. otherwise, unexpected result will occur.
ssd0817 series rev 1.3 01/2003 solomon 21 i 2 c-bus write data and read register status the i 2 c-bus interface gives access to write data and command into the device. please refer to figure 7 for the write mode of i 2 c-bus in chronological order. figure 7 i 2 c-bus data format write mode 1) the master device initiates the data communication by a start condition. the definition of the start condition is shown in figure 8 on page 22. the start condition is established by pulling the sda from high to low while the scl stays high. 2) the slave address is following the start condition for recognition use. for the ssd0817, the slave address is either ?b0111100? or ?b0111101? by changing the sa0 to high or low. 3) the write mode is established by setting the r/ w bit to logic ?0?. 4) an acknowledgement signal will be generated after receiving one byte of data, including the slave address and the r/ w bit. please refer to the figure 9 on page 22 for the graphical representation of the acknowledge signal. the acknowledge bit is defined as the sda line is pulled down during the high period of the acknowledgement related clock pulse. 5) after the transmission of the slave address, either the control byte or the data byte may be sent across the sda. a control byte mainly consists of co and d/ c bits following by six ?0? ?s. a. if the co bit is set as logic ?0?, the transmission of the following information will contain data bytes only. 0 1 1 1 1 0 sa0 p slave address m 0 words n 0 bytes msb ??????.lsb 1 byte write mode slave address ssd0817 slave address read mode r/w d/c co a ck a ck control b y te data b y te a ck co d/c control b y te a ck data b y te a ck s 0 1 1 1 1 0 0 1 1 1 1 0 s sa0 a ck status bytes a ck p sa0 r/w co d/c a ck control b y te note: co ? continuation bit d/ c ? data / command selection bit ack ? acknowledgement sa0 ? slave address bit r/ w ? read / write selection bit s ? start condition / p ? stop condition 0 0 0 0 0 0 0 1 1 1 1 0 r/w
solomon rev 1 . 3 01/2003 ssd0817 series 22 data output by receiv er data output by transmitter scl from master s start condition clock pulse for acknowledgement 1 8 9 non-acknowled g e 2 acknowled g e s start condition sda scl p stop condition sda scl t dh , start t ds , stop b. the d/ c bit determines the next data byte is acted as a command or a data. if the d/ c bit is set to logic ?0?, it defines the following data byte as a command. if the d/ c bit is set to logic ?1?, it defines the following data byte as a data which will be stored at the gddram. the gddram column address pointer will be increased by one automatically after each data write. 6) acknowledge bit will be generated after receiving each control byte or data byte. 7) the write mode will be finished when a stop condition is applied. the stop condition is also defined in figure 8 on page 22. the stop condition is established by pulling the ?sda in? from low to high while the ?scl? stays high. figure 8 definition of the start and stop condition figure 9 definition of the acknowledgement condition please be noted that the transmission of the data bit has some limitations. 1. the data bit, which is transmitted during each scl pulse, must keep at a stable state within the ?high? period of the clock pulse. please refer to the figure 10 for graphical representations. except in start or stop conditions, the data line can be switched only when the scl is low. 2. both the data line (sda) and the clock line (scl) should be pulled up by external resistors.
ssd0817 series rev 1.3 01/2003 solomon 23 figure 10 definition of the data transfer condition read mode (read status register) 1) the master device firstly initiates the data communication by a start condition. the definition of the start condition is shown in figure 8 on page 22. 2) the slave address is following the start condition for recognition use. for the ssd0817, the slave address is either ?b0111100? or ?b0111101?. 3) the read mode is established by setting r/ w bit to logic ?1?. the read mode allows the mcu to monitor the internal status of the chip. 4) an acknowledgement signal will be generated after sending one byte of data, including the slave address and the r/ w bit. please refer to the figure 9 on page 22 for the graphical representation of the acknowledge signal. 5) the status of the register will be read at the next status byte. please refer to the table 9 for the explanation of the status byte. 6) the read mode will be finished when a stop condition is applied. the stop condition is also defined in figure 8 on page 22. s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 status register read s 7 =0: indicates the driver is ready for command. s 7 =1: indicates the driver is busy. s 6 =0: indicates reverse segment mapping with column address. s 6 =1: indicates normal segment mapping with column address. s 5 =0: indicates the display is on. s 5 =1: indicates the display is off. s 4 =0: initialization is completed. s 4 =1: initialization process is in progress after res or software reset. s 3 s 2 s 1 s 0 = 1001, the 4-bit is fixed to 1001 which could be used to identify as solomon-systech device. table 9 - read command table (r/ w bit =1) change of data is allowed data line is stable; data is valid sda scl
solomon rev 1 . 3 01/2003 ssd0817 series 24 command descriptions set lower column address this command specifies the lower nibble of the 8-bit column address of the display data ram. the column address will be increased by each data access after it is pre-set by the mcu. set higher column address this command specifies the higher nibble of the 8-bit column address of the display data ram. the column address will be increased by each data access after it is pre-set by the mcu. set internal regulator resistors ratio this command is to enable any one of the eight internal resistor sets for different regulator gain when using internal regulator resistor network (irs pin pulled high). in other words, this command is used to select which contrast curve from the eight possible selections. please refer to functional block descriptions section for detail calculation of the lcd driving voltage. set power control register this command turns on/off the various power circuits associated with the chip. there are three related power sub-circuits could be turned on/off by this command. internal voltage booster is used to generate the negative voltage supply (v ee ) from the voltage input (v ss1 - v dd ). an external negative power supply is required if this option is turned off. internal regulator is used to generate the lcd driving voltage, v l6 , from the negative power supply, v ee . output op-amp buffer is the internal divider for dividing the different voltage levels (v l2 , v l3 , v l4 , v l5 ) from the internal regulator output, v l6 . external voltage sources should be fed into this driver if this circuit is turned off. set display start line this command is to set display start line register to determine starting address of display ram to be displayed by selecting a value from 0 to 63. with value equals to 0, d0 of page 0 is mapped to com0. with value equals to 1, d1 of page0 is mapped to com0 and so on. display start line values of 0 to 63 are assigned to page 0 to 7. please refer to table 4 on page 12 as an example for display start line set to 56 (38h). set contrast control register this command adjusts the contrast of the lcd panel by changing the lcd driving voltage, v l6 , provided by the on-chip power circuits. v l6 is set with 64 steps (6-bit) in the contrast control register by a set of compound commands. see figure 11 for the contrast control flow. figure 11 - contrast control flow changes complete? no yes set contrast control register contrast level data
ssd0817 series rev 1.3 01/2003 solomon 25 set segment re-map this command changes the mapping between the display data column addresses and segment drivers. it allows flexibility in mechanical layout of lcd glass design. please refer to table 4 on page 12 for example. set lcd bias this command is used to select a suitable bias ratio required for driving the particular lcd panel in use. the selectable values of this command for 64 mux are 1/9 or 1/7. for other bias ratio settings, extended commands should be used. set entire display on/off this command forces the entire display, including the icon row, to be illuminated regardless of the contents of the gddram. in addition, this command has higher priority than the normal/inverse display. this command is used together with ?set display on/off? command to form a compound command for entering power save mode. see ?set power save mode? later in this section. set normal/inverse display this command turns the display to be either normal or inverse. in normal display mode, a ram data of 1 indicates an illumination on the corresponding pixel. in inverse display mode, a ram data of 0 will turn on the pixel. it should be noted that the icon line is not affect. the icon line is not inversed by this command. set display on/off this command is used to turn the display on or off. when display off is issued with entire display is on, power save mode will be entered. see ?set power save mode? later in this section for details. set page address this command enters the page address from 0 to 8 to the ram page register for read/write operations. please refer to table 4 on page 12 for detail mapping. set com output scan direction this command sets the scan direction of the com output allowing layout flexibility in lcd module assembly. see table 4 on page 12 for the relationship between turning on or off of this feature. in addition, the display will have immediate effect once this command is issued. that is, if this command is sent during normal display, the graphic display will have vertical flipping effect. set read-modify-write mode this command puts the chip in read-modify-write mode in which: 1. the column address is saved before entering the mode 2. the column address is increased only after display data write but not after display data read. this read-modify-write mode is used to save the mcu ?s loading when a very portion of display area is being updated frequently. as reading the data will not change the column address, it could be get back from the chip and do some operation in the mcu. then the updated data could be written back to the gddram with automatic address increment. after updating the area, ?set end of read-modify-write mode? is sent to restore the column address and ready for next update sequence.
solomon rev 1 . 3 01/2003 ssd0817 series 26 software reset issuing this command causes some of the chip?s internal status registers to be initialized: read-modify-write mode is off static indicator is turned off display start line register is cleared to 0 column address counter is cleared to 0 page address is cleared to 0 normal scanning direction of the com outputs internal regulator resistors ratio is set to 4 contrast control register is set to 20h set end of read-modify-write mode this command relieves the chip from read-modify-write mode. the column address before entering read-modify-write mode will be restored no matter how much modification during the read-modify- write mode. set indicator on/off this command turns on or off the static indicator driven by the m and mstat pins. when the ?set indicator on? command is sent, the second command byte ?indicator display mode? must be followed. however, the ?set indicator off? command is a single byte command and no second byte command is required. the status of static indicator also controls whether standby mode or sleep mode will be entered, after issuing the power save compound command. see ?set power save mode? later in this section. nop a command causing the chip takes no operation. set test mode this command forces the driver chip into its test mode for internal testing of the chip. under normal operation, users should not use this command. set power save mode the standby or sleep mode operation should be executed by a compound command. the compound command is composed of ?set display on/off? and ?set entire display on/off? commands. when the ?set entire display? is on and the ?set display? is off, either standby mode or sleep mode will be entered. the status of the static indicator will determine which power save mode is entered. if static indicator is off, the sleep mode will be entered: internal oscillator and lcd power supply circuits are stopped segment and common drivers output v dd level the display data and operation mode before sleep are held internal display ram can still be accessed if the static indicator is on, the chip enters standby mode, which is similar to sleep mode except addition with: internal oscillator is on static drive system is on please also be noted that during standby mode, if the ?software reset? command is issued, sleep mode will be entered. both power save modes can be exited by the issue of a new software command or by pulling low at hardware pin res . extended commands these commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip.
ssd0817 series rev 1.3 01/2003 solomon 27 set multiplex ratio this command switches default multiplex ratio to any multiplex mode from 2 to the maximum multiplex ratio (por value), including the icon line. max. mux ratio: 65 the chip pins row0-row63 will be switched to corresponding com signal output, see table 10 on page 29 for examples of 18 multiplex (including icon line) settings with and without 7 lines display offset for different mux. remarks: after changing the display multiplex ratio, the bias ratio may be adjusted in order to make display contrast consistent. set bias ratio except the 1/4 bias, all other available bias ratios could be selected using this command plus the ?set lcd bias? command. for detail setting values and por default, please refer to the extended command table, table 8 on page 19. set temperature coefficient (tc) value one out of four different temperature coefficient settings is selected by this command in order to match various liquid crystal temperature grades. please refer to the extended command table, table 8 on page 19, for detailed tc values. modify oscillator frequency the oscillator frequency can be fine tuned by applying this command. since the oscillator frequency will be affected by some other factors, this command is not recommended for general usage. please contact solomon-systech limited application engineers for more detail explanation on this command. set 1/4 bias ratio this command sets the bias ratio directly to 1/4. this bias ratio is especially designed for use in under 12 mux display. in order to restore to other bias ratio, this command must be executed, with lsb=0, before the ?set multiplex ratio? or ?set lcd bias? command is sent. set total frame phases the total number of phases for one display frame is set by this command. the static icon is generated by overlapping the m and the mstat signals. these two pins output either v ss or v dd at same frequency but with phase different. to turn on the static icon, 3 phases overlapping is applied to these signals, while 1 phase overlapping is given to the ?off ?status. with the increase in the total number of phases in a single frame, the overlapping time decreases. thus the lower the effective driving voltage at the static icon on the lcd panel.
solomon rev 1 . 3 01/2003 ssd0817 series 28 set display offset this command should be sent only when the multiplex ratio is set less than the default value. when a lesser multiplex ratio is set, the display will be mapped in the middle (y-direction) of the lcd, see the no offset columns on table 10 on page 29. use this command could move the display vertically within the 64 commons. to make the reduced-mux com 0 (com 0 after reducing the multiplex ratio) towards the row 0 direction for l lines, the 6-bit data in second command should be given by l. an example for 7 lines moving towards to com0 direction is given on table 10 on page 29. to move in the other direction by l lines, the 6-bit data should be given by 64-l. please note that the display is confined within the default multiplex value. that is the maximum value of l is given by the half of the default value minus the reduced-multiplex ratio. for an odd display mux after reduction, moving away from row 0 direction will has 1 more step. enable band gap reference circuit this command enables or disables the band gap reference circuit. it should be noticed that this command should be executed if divider is used without capacitor at vl2 to vl5. there are four selections on the band gap clock period. we recommended to set the band gap clock period to 200ms in normal operation.
ssd0817 series rev 1.3 01/2003 solomon 29 48 mux mode 54 mux mode 32 mux mode 64 mux mode no offset 7 lines offset no offset 7 lines offset no offset 7 lines offset no offset 7 lines offset row0 x x x x x com0 x x row1 x x x x x com1 x x row2 x x x x x com2 x x row3 x x x x x com3 x x row4 x x x x x com4 x x row5 x x x x x com5 x x row6 x x x x x com6 x x row7 x x x x com0 com7 x x row8 x com0 x x com1 com8 x x row9 x com1 x x com2 com9 x x row10 x com2 x x com3 com10 x x row11 x com3 x com0 com4 com11 x x row12 x com4 x com1 com5 com12 x x row13 x com5 x com2 com6 com13 x x row14 x com6 x com3 com7 com14 x x row15 com0 com7 x com4 com8 com15 x x row16 com1 com8 x com5 nc nc x com0 row17 com2 com9 x com6 nc nc x com1 row18 com3 com10 com0 com7 nc nc x com2 row19 com4 com11 com1 com8 nc nc x com3 row20 com5 com12 com2 com9 nc nc x com4 row21 com6 com13 com3 com10 nc nc x com5 row22 com7 com14 com4 com11 nc nc x com6 row23 com8 com15 com5 com12 nc nc com0 com7 row24 nc nc com6 com13 nc nc com1 com8 row25 nc nc com7 com14 nc nc com2 com9 row26 nc nc com8 com15 nc nc com3 com10 row27 nc nc nc nc nc nc com4 com11 row28 nc nc nc nc nc nc com5 com12 row29 nc nc nc nc nc nc com6 com13 row30 nc nc nc nc nc nc com7 com14 row31 nc nc nc nc nc nc com8 com15 row32 com9 com16 com9 com16 com9 com16 com9 com16 row33 com10 x com10 x com10 x com10 x row34 com11 x com11 x com11 x com11 x row35 com12 x com12 x com12 x com12 x row36 com13 x com13 x com13 x com13 x row37 com14 x com14 x com14 x com14 x row38 com15 x com15 x com15 x com15 x row39 com16 x com16 x com16 x com16 x row40 x x x x x x x x row41 x x x x x x x x row42 x x x x x x x x row43 x x x x x x x x row44 x x x x x x x x row45 x x x x x x x x row46 x x x x x x x x row47 x x x x x x x x row48 x x x x nc nc x x row49 x x x x nc nc x x row50 x x x x nc nc x x row51 x x x x nc nc x x row52 x x x x nc nc x x row53 x x x x nc nc x x row54 x x x x nc nc x x row55 x x x x nc nc x x row56 nc nc x x nc nc x x row57 nc nc x x nc nc x x row58 nc nc x x nc nc x x row59 nc nc nc nc nc nc x x row60 nc nc nc nc nc nc x x row61 nc nc nc nc nc nc x x row62 nc nc nc nc nc nc x x row63 nc nc nc nc nc nc x x table 10 - row pin assignment for com signals for ssd0817 in an 18 mux display (including icon line) without/with 7 lines display offset towards row0 note: x-row pin will output non-selected com signal
solomon rev 1 . 3 01/2003 ssd0817 series 30 maximum ratings table 11 - maximum ratings (voltage referenced to v ss ) symbol parameter value unit v dd -0.3 to +4.0 v v ee supply voltage 0 to ?12.0 v vin input voltage vss-0.3 to vdd+0.3 v i current drain per pin excluding v dd and v ss 25 ma t a operating temperature -30 to +85 o c t stg storage temperature -65 to +150 o c maximum ratings are those values beyond which damages to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that vin and vee be constrained to the range vss < or = (vin or vout) < or = vdd. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either vss or vdd). unused outputs must be left open. this device may be light sensitive. caution should be taken to avoid exposure of this device to any light source during normal operation. this device is not radiation protected.
ssd0817 series rev 1.3 01/2003 solomon 31 dc characteristics table 12 - dc characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = -30 to 85 c) symbol parameter test condition min typ max unit v dd logic circuit supply voltage range recommend operating voltage possible operating voltage 2.4 2.7 3.5 v v i ac access mode supply current drain (v dd pins) v dd = 2.7v, voltage generator on, 4x dc-dc converter enabled, write accessing, tcyc =3.3mhz, typ. osc. freq., display on, no panel attached. - 480 600 a i dp1 display mode supply current drain (v dd pins) v dd = 2.7v, v ee = -8.1v, voltage generator disabled, r/ w( wr ) halt, typ. osc. freq., display on, v l6 - v dd = -9v, no panel attached. - 50 100 a i dp2 display mode supply current drain (v dd pins) v dd = 2.7v, v ee = -8.1v, voltage generator on, 4x dc-dc converter enabled, r/ w( wr ) halt, typ. osc. freq., display on, v l6 - v dd = -9v, no panel attached. - 120 200 a i sb standby mode supply current drain (v dd pins) v dd = 2.7v, lcd driving waveform off, typ. osc. freq., r/ w( wr ) halt. - 5 10 a i sleep sleep mode supply current drain (v dd pins) v dd = 2.7v, lcd driving waveform off, oscillator off, r/ w( wr ) halt. - 1 5 a v ee lcd driving voltage generator output (v ee pin) display on, voltage generator enabled, dc-dc converter enabled, typ. osc. freq., regulator enabled, divider enabled. -12.0 - -2.4 v v lcd lcd driving voltage input (v ee pin) voltage generator disabled. -12.0 - -2.4 v v oh1 logic high output voltage iout=-100ma 0.9*v dd - v dd v v ol1 logic low output voltage iout=100ma 0 - 0.1* v dd v v l6 lcd driving voltage source (v l6 pin) regulator enabled (v l6 voltage depends on int/ext contrast control) v ee -0.5 - v dd v v l6 lcd driving voltage source (v l6 pin) regulator disable - floating - v v ih1 logic high input voltage 0.8*v dd - v dd v v il1 logic low input voltage 0 - 0.2* v dd v
solomon rev 1 . 3 01/2003 ssd0817 series 32 - 1/a*v l6 - v - 2/a*v l6 - v - (a-2)/a *v l6 - v - (a-1)/a *v l6 - v v l2 v l3 v l4 v l5 v l6 lcd display voltage output (v l2 , v l3 , v l4 , v l5 , v l6 pins) voltage reference to v dd , bias divider enabled, 1:a bias ratio - v l6 - v v l3 - v dd v v l4 - v l2 v v l5 - v l3 v v l6 - v l4 v v l2 v l3 v l4 v l5 v l6 lcd display voltage input (v l2 , v l3 ,v l4 , v l5 , v l6 pins) voltage reference to v dd , external voltage generator, bias divider disabled -12v - v l5 v i oh logic high output current source vout = v dd -0.4v 50 - - a i ol logic low output current drain vout = 0.4v - - -50 a i oz logic output tri-state current drain source -1 - 1 a i il /i ih logic input current -1 - 1 a c in logic pins input capacitance - 5 7.5 pf ? v l6 variation of v l6 output (v dd is fixed) regulator enabled, internal contrast control enabled, set contrast control register = 0 -3 0 3 % tc0 temperature coefficient compensation flat temperature coefficient (por) 0 -0.07 -0.11 %/ o c tc2 temperature coefficient 2* -0.11 -0.13 -0.15 %/ o c tc4 temperature coefficient 4* -0.15 -0.26 -0.28 %/ o c tc7 temperature coefficient 7* voltage regulator enabled -0.28 -0.29 -0.30 %/ o c the formula for the temperature coefficient is: tc(%) = v ref at 50 o c ? v ref at 0 o c x 1 x 100 % 50 o c ? 0 o c v ref at 25 o c
ssd0817 series rev 1.3 01/2003 solomon 33 ac characteristics table 13 - ac characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = -30 to 85 c) symbol parameter test condition min typ max unit fosc oscillation frequency of display timing generator 64 mux mode 54 mux mode internal oscillator enabled (default), vdd = 2.7v remark: oscillator frequency vs. temperature change (-20c to 70c): -0.5%/c * 15.9 26.4 18.7 31.5 25.7 42.72 khz khz f frm frame frequency 64 mux mode 54 mux mode 48 mux mode 32 mux mode 104 x 64 graphic display mode, display on, internal oscillator enabled 104 x 64 graphic display mode, display on, internal oscillator disabled, external clock with freq., fext, feeding to cl pin. 104 x 54 graphic display mode, display on, internal oscillator enabled 104 x 54 graphic display mode, display on, internal oscillator disabled, external clock with freq., fext, feeding to cl pin. 104 x 48 graphic display mode, display on, internal oscillator enabled 104 x 48 graphic display mode, display on, internal oscillator disabled, external clock with freq., fext, feeding to cl pin. 104 x 32 graphic display mode, display on, internal oscillator enabled 104 x 32 graphic display mode, display on, internal oscillator disabled, external clock with freq., fext, feeding to cl pin. fosc 4x65 fext 4x65 fosc 8x54 fext 8x54 fosc 8x49 fext 4x49 fosc 8x33 fext 4x33 hz hz hz hz hz hz hz hz remarks: fext stands for the frequency value of external clock feeding to the cl pin fosc stands for the frequency value of internal oscillator frequency limits are based on the software command: set multiplex ratio to 32/48/54/64 table 14 - i 2 c-bus timing characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = 25 c)
solomon rev 1 . 3 01/2003 ssd0817 series 34 symbol parameter min typ max unit f scl i 2 c-bus clock frequency, scl 0 - 500 khz t clkl i 2 c-bus clock low period, scl 960 - - ns t clkh i 2 c-bus clock high period, scl 960 - - ns t dsw i 2 c-bus data setup time, sda 120 - - ns t dhw i 2 c-bus data hold time, sda 0 - 0.98 us t r rise time between sda & scl 32 - 350 ns t f fall time between sda & scl 32 - 350 ns c bus capacitive loadings at each i 2 c-bus channel - - 400 pf t dh, start i 2 c-bus setup time, start condition 180 - - ns t ds, stop i 2 c-bus hold time, stop condition 180 - - ns
ssd0817 series rev 1.3 01/2003 solomon 35 symbol parameter min typ max unit t cycle clock cycle time 2.0 - - us t dsw write data setup time 120 - - ns t dhw write data hold time 0 - 0.98 us t clkl clock low time 960 - - ns t clkh clock high time 960 - - ns t r rise time - 200 350 ns t f fall time - 200 350 ns t dh, start hold time, start condition 0.18 2.5 - us t ds, stop setup time, stop condition 0.18 2.5 - us table 15 - interface timing characteristics (vdd - vss = 2.4 to 3.5v, ta = 25c) figure 12 ? iic data bus interface driving waveform t dh, sta rt t ds, stop t dsw t dhw t r t f t clkh t clkl t cyc le sda scl
solomon rev 1 . 3 01/2003 ssd0817 series 36 application examples logic pin connections not specified above: pins connected to vdd: irs, cs2, m/ s , cls, iic2, test0 - test7 pins connected to vss: vss1, 1 cs , iic1 pins floating: dof , cl, t0-t6 pin connected to either vdd or vss by user defined: c0, c1 and sa0 sda in & scl should be pulled high by a pair of resistors: 100k ohm figure 13 - application circuit of 104 x 64plus an icon line using ssd0817, configured with: external vee, internal regulator, divider mode enabled (command: 2b), iic data bus interface, internal oscillator and master mode display panel size 104 x 64 + 1 icons line ssd0817ic 64 mux seg0................................seg103 segment remapped [command: a1] icons com0 : : com10 com11 : : com30 com31 com32 com33 : : : : com63 icons com44 com45 : : : : : com63 icons com10 com11 : : com18 com19 : : com30 com31 com43.......com32 seg 103............................................................................seg0 icons com0 .... remapped com scan directiion [command: c8] remapped com scan directiion [command: c8] /res sda in scl vss[gnd] vee external vneg = -9.5v sda out capacitor value: 0.1uf ~ 0.47 uf vdd = 2.775v vl2 vl3 vl4 vl5 vl6
ssd0817 series rev 1.3 01/2003 solomon 37 logic pin connections not specified above: pins connected to v dd :, m/ s , cs2, cls, iic2, irs, test0-test7 pins connected to v ss : v ss1 , iic1 , 1 cs pins floating: dof , cl, t0 - t6 pin connected to either vdd or vss by user defined :sa0 pin connected together: sda in & sda out sda in and scl should be pulled high by a pair of resistors: value = 100 k ohm figure 14 - application circuit of 104 x 64plus an icon line using ssd0817, configured with all internal power control circuit enabled, fully iic data bus interface, internal oscillator and master mode. display panel size 104 x 64 + 1 icons line ssd0817 ic 64 mux (die face up) seg0.................................seg103 segment remapped [command: a1] icons com0 : : com10 com11 : : com30 com31 com32 com33 : : : : com63 icons com44 com45 : : : : : com63 icons com10 com11 : : com18 com19 : : com30 com31 com43..........com32 seg103........................................................................seg0 icons com0 ... remapped com scan directiion [command: c8] remapped com scan directiion [command: c8] vss [gnd] 0.47 - 1uf x 5 5x boosting vss vee c3n c1p c1n c2n c2p c4n sdain scl sdaout optional for sdain & sdaout are shorted /res capacitor value: 0.1uf ~ 0.47 uf vdd = 2.775v vl2 vl3 vl4 vl5 vl6
solomon rev 1 . 3 01/2003 ssd0817 series 38 logic pin connections not specified above: pins connected to v dd : cs2, m/ s , cls, iic2, d2, d3, d6, d7, irs pins connected to v ss : v ss1 , iic1 , test0 - test7, 1 cs pins floating: dof , cl, t0 - t6 pin connected to either vdd or vss by user defined :sa0 pin connected together: sdain & sdaout sda in and scl should be pulled high by a pair of resistors: value = 100 k ohm figure 15 - application circuit of 104 x 64plus an icon line using ssd0817, configured with all external power control circuit enabled, fully iic data bus interface, internal oscillator, internal contrast gain and master mode. (minimum pin outlets) display panel size 104 x 64 + 1 icons line ssd0817 ic 64 mux (die face up) seg0.................................seg103 segment remapped [command: a1] icons com0 : : com10 com11 : : com30 com31 com32 com33 : : : : com63 icons com44 com45 : : : : : com63 icons com10 com11 : : com18 com19 : : com30 com31 com43.......com32 seg103..............................................................................seg0 icons com0 .... remapped com scan directiion [command: c8] remapped com scan directiion [command: c8] capacitor value: 0.1uf ~ 0.47 uf vss [gnd] vdd = 2.775v vl2 sdain scl /res vee = -9.5v vl3 vl4 vl5 vl6
ssd0817 series rev 1.3 01/2003 solomon 39 initialization routine command (hex) (refer to figure 11: all internal power control circuit enable) command (hex) (refer to figure 12: external v ee , internal regulator and divider enable) description 1 e2 e2 software reset 2 2f 2b set power control register 3 24 24 set internal resistor gain = 24h 4 81 20 81 20 set contrast level = 20h 5 d6 2d d6 2d enable band gap reference circuit set band gap clock period = 200ms 6 a0 a0 set column address is map to seg0 7 c0 c0 set row address is map to com0 8 a4 a4 set entire display on/off = normal display 9 a6 a6 set normal / reverse display = normal display 10 af af set display on example internal booster, regulator and divider are enabled. v op = approx. -8.735v with reference to v dd external booster, internal regulator and divider are enabled. v op = approx. -8.593v with reference to v dd
solomon rev 1 . 3 01/2003 ssd0817 series 40 solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitab ility of its pr oducts for any particular purpose, nor does solomon systech assume any liab ility arising out of the application or use of any product or circuit, and specifically disclaims any and all liab ility, including wit hout limitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as compo nents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applic ation in which the failure of the solomon systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon sys- tech products for any such unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its offic es, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was negligent regarding the design or manufacture of the part.

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